1. Field of the Invention
This invention relates to time-resolved emission for timing and voltage measurement. More specifically, this invention relates to using time-resolved emission to measure timing perturbation and voltage modulation signals inside an integrated circuit.
2. Description of Related Art
Time-resolved emission (TRE) is commonly used for circuit debug and advanced timing-related failure analysis. Established application areas include localization of resistive interconnects, timing contention, circuit debug, clock distribution skew analysis, and other timing-related fault isolation techniques.
The basic concepts of time-resolved emission have been covered extensively in the prior art. The carriers responsible for the source-drain current in a transistor can emit photons if they are sufficiently excited. Some of these photons are in an energy band which can be detected by time-resolved single-photon detectors. When a normally-operating gate in a properly designed CMOS circuit switches, the carriers are briefly saturated and thus have an elevated probability of emitting a detectable infra-red photon. These photons are accumulated by a time-resolved system to measure the timing behavior of a device. The probability of detecting a photon in a single switching event is small, so the stimulus is looped many times and the photons time stamps are relative to the start of the loop.
Circuit jitter limits the performance of many high-speed circuits. Jitter can limit bit error rate (BER) in serial communication circuits, including PCI Express, Serial ATA, Gigabit Ethernet, and InfiniBand. It also limits the clock frequency of microprocessors, advanced chipsets, graphics processors, and other circuits relying on phase-locked loops (PLLs) and clock distribution networks.
Conventional electrical jitter measurements on internal nodes require gaining physical access to metal lines, often using focussed ion beam (FIB) to create access to a metal line contact point, and an electrical probe of some kind to make mechanical ohmic contact to that contact point. While such measurement enable real-time measurements of jitter timing, the mechanical probing process can load a circuit so much that it alters the electrical behavior of the circuit. For example, a typical gate capacitance is less than 10 fF/μm width, while even a very small mechanical probe can have capacitance of 0.02 to 0.5 pF, i.e, significantly larger than the gate capacitance.
Another prior art technique is to use design-for-test (DFT) features to induce or measure time-dependant voltage information. This is possible in some cases, but the high area penalty precludes its use except for a few nodes. Further, nodes which have been designed carefully using DFT features are not the ones that require extensive debug. Thus, non-invasive jitter measurements can be quite valuable.
The source of timing jitter is local voltage noise. The voltage noise is either random (such as Nyquist noise caused by local impedance) or is deterministic (caused by pickup from another part of the circuit). Deterministic noise is either asynchronous with the test loop (caused by a voltage noise source uncorrelated with the stimulus) or is synchronous. Both asynchronous and random jitter widen the peaks detected by the TRE system because the TRE system requires many loops to acquire a timing signal. On the other hand, deterministic, synchronous jitter causes a variation in the timing delay between TRE peaks, but not broadening of the peaks.
Improved means are needed in the art to enable non-invasive measurement of dynamic local power supply voltage variations and synchronous timing jitter induced by the voltage variations.